9/14 ＜ECTC2023での発表を解説＞ 先端半導体パッケージング・実装技術の研究開発動向

東北大学　大学院工学研究科 機械機能創成専攻　准教授　福島誉史 氏

【講師紹介】
2001年4月～2003年3月 株式会社ピーアイ技術研究所 技術顧問

2003年4月～2004年7月 東北大学ベンチャービジネスラボラトリー 講師

（中核的研究機関研究員）

2004年8月～2010年3月 東北大学　大学院工学研究科　バイオロボティクス専攻 助手／助教

2010年4月～2015年3月 東北大学未来科学技術共同研究センター 准教授

2015年4月～2016年7月 東北大学 大学院工学研究科　バイオロボティクス専攻 准教授
2016年3月～2017年7月 米国UCLA, Electrical Engineering Department, Visiting Faculty
2016年8月～現在に至る

　昨今、特に話題を集める半導体パッケージングですが、これに関連した数ある国際会議の中でも最も大きく最新の技術が発表されるのがECTC (Electronic Components and Technology Conference)です。
　今回のセミナーでは、半導体パッケージングの最新動向を紹介し、2023年6月に終えたECTC2023の中からチップレット／RDLインターポーザ／Siブリッジ／FOWLP 、およびハイブリッド接合を中心にハイライトを行います。ECTC2023の総発表件数379件（ポスター127件含む）から68件の注目発表をピックアップして解説する予定です。

１．ECTCの紹介と最近の研究動向、および用語の説明
　1.1 ECTCの発表件数の推移や国別／研究機関別投稿状況
　1.2 3D-IC/TSV技術（Via-middle vs. Via-last, Wafer-to-Wafer vs. Chip-to-Wafer他）
　1.3 インターポーザの分類（2.5D vs. 有機RDL vs. ガラス）
　1.4 CoWoS (Chip-on-Wafer-on-Substrate)とFOWLP（Fan-Out Wafer-Level Packaging）
　1.5 ハイブリッド接合の概要

２．チップレット／RDLインターポーザ／ブリッジ／FOWLP　13件
Session 1: Heterogeneous Chiplet Integration
・Paper 1. Ultra High Density Low Temperature SoIC with Sub-0.5 µm Bond

　Pitch (TSMC)
・Paper 2. Process Integration of Photonic Interposer for Chiplet-Based 3D

　Systems (CEA-LETI)
・Paper 4. Design Space Exploration (DSE) for over-136 GB/s IO Bandwidth

　with LPDDR5X SDRAM Packages on SOC Package in 200 mm³ (Samsung)
・Paper 5. 3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform

　with Thru-Silicon Redistribution Layer (IME/ Qorvo)
・Paper 6. Same Size Mold Chase Technology for Effective Stack Die

　Architectures (Intel/Towa)
・Paper 7. A Novel Chiplet Integration Architecture Employing Pillar-Suspended

　Bridge with Polymer Fine-Via Interconnect (ULVAC/Taiyo Ink/Tohoku

　University/Osaka University/AOI Electronics/Oume Electronics/Sumitomo

　Bakelite/Tokyo Tech)

Session 13: Wafer/Panel-Level and Advanced Substrate Technologies
・Paper 1. Supercarrier Redistribution Layers to Realize Ultra Large 2.5D Wafer

　Scale Packaging by CoWoS (TSMC)
・Paper 3. Fabrication of Two-Types Panel-Level Interposers with Fine Cu

　Wirings and Outstanding Electrical Reliability (Resonac)
・Paper 5. Signal Integrity of 2-µm-Pitch RDL Interposer for High-Performance

　Signal Processing in Chiplet-Based System (DNP)

Session 21: Fine-Pitch and Intermetallic Considerations in Advanced

Solder Interconnections
・Paper 4. Heterogeneous Integration on Organic Interposer Substrate with

　fine-pitch RDL and 40 micron pitch Micro-bumps (IBM)

Session 25: Next Generation High-Performance Computing Architectures
・Paper 1. CoWoS(-L) Architecture Evolution for Next Generation HPC on 2.5D

　System in Package (TSMC)

Session 32: Thermo-Mechanical Modelling and Characterization
・Paper 7. Fan-Out Embedded Bridge with TSV (FO-EB-T) Package

　Characterization and Evaluation(Siliconware Precision Industries)

Session 33: Advances in RDL, Via, and TSV Technologies for Chiplet

Integration
・Paper 4. Ultra Fine Pitch RDL (UFPRDL) Using Polymer Dual Damascene

　Processing (imec)

３．ハイブリッド接合　50件
Session 1: Heterogeneous Chiplet Integration
・Paper 3. Aggressive Pitch Scaling (sub-0.5 µm) of W2W Hybrid Bonding

　Through Process Innovations(AMAT/EVG)

Session 3: Advancements in Copper/Silicon-Oxide Hybrid Bonding
・Paper 1. A Study on the Surface Activation of Cu and Oxide for Hybrid

　Bonding Joint Interface (Samsung)
・Paper 2. Fine Pitch Die-to-Wafer Hybrid Bonding (Adeia)
・Paper 3. Direct Die to Wafer Cu Hybrid Bonding for Volume

　Production (ASMPT/EVG)
・Paper 4. Demonstration of a Wafer Level Face-To-Back (F2B) Fine Pitch

　Cu-Cu Hybrid Bonding with High Density TSV for 3D Integration

　Applications (CEA-LETI)

・Paper 5. Cu-Cu Wiring: The Novel Structure of Cu-Cu Hybrid Bonding (Sony)
・Paper 6. New Cu "Bulge-Out" Mechanism Supporting Sub-Micron Scaling of

　Hybrid Wafer-to-Wafer Bonding(imec)

・Paper 7. Electrical Analysis of Wafer-to-Wafer Copper Hybrid Bonding at

　Sub-Micron Pitches (TEL America)

Session 8: Novel Reliability Test Methods
・Paper 4. Chip Level Evaluation of Wafer-to-Wafer Direct Bonding Strength with

　Bending Test (Samsung) 

Session 9: Innovations in Copper Chip-to-Wafer Bonding
・Paper 1. Critical Challenges with Copper Hybrid Bonding for Chip-to-Wafer

　Memory Stacking (Micron)
・Paper 2. Development of Copper Thermal Coefficient for Low Temperature

　Hybrid Bonding (AMAT)
・Paper 3. Impact of Plasma Activation on Copper Surface Layer for Low

　Temperature Hybrid Bonding(TEL America)
・Paper 4. Investigation of Cu-Cu Direct Bonding Process Utilized by High

　Porosity and Nanocrystal Structure(Mitsubishi Materials)
・Paper 5. A High Throughput Two-Stage Die-to-Wafer Thermal Compression

　Bonding Scheme for Heterogeneous Integration (UCLA)
・Paper 7. Towards Selective Cobalt Atomic Layer Deposition for Chip-to-Wafer

　3D Heterogeneous Integration(Georgia Tech/UCSD)

Session 14: Advances in Heterogeneous Integration Bonding Technology
・Paper 1. Characterization of 300 mm Low Temperature SiCN PVD Films for

　Hybrid Bonding Application(Intel/Evatec)
・Paper 3. Cu Damascene Process on Temporary Bonded Wafers for Thin Chip

　Stacking Using Cu-Cu Hybrid Bonding (IME/AMAT)
・Paper 4. A New Adhesive for CoW Cu-Cu Hybrid Bonding with High Throughput

　and Room Temperature Pre-Bonding (Mitsui Chemicals)
・Paper 5. Low-Temperature and Pressureless Cu-to-Cu Bonding by Electroless

　Pd Plating Using Microfluidic System (National Taiwan University/ASE)

Session 19: Advances in 3D Integration and Hybrid Bonding
・Paper 1. Thermal Improvement of HBM with Joint Thermal Resistance Reduction

　for Scaling 12 Stacks and Beyond (Samsung)
・Paper 4. Reliability Performance on Fine-Pitch SoIC™ Bond (TSMC)
・Paper 5. Development of 4 Die Stack Module Using Hybrid Bonding Approach (IME)
・Paper 6. Impact of Dielectric and Copper Via Design on Wafer-to-Wafer Hybrid

　Bonding (Fraunhofer ENAS)
・Paper 7. Voids-Free Die-Level Cu/ILD Hybrid Bonding (IBM/ASMPT)

Session 25: Next Generation High-Performance Computing Architectures
・Paper 5. Die to Wafer Hybrid Cu Bonding for Fine Pitch 3D-IC

　Applications (Samsung)
・Paper 6. C2W Hybrid Bonding Interconnect Technology for Higher Density and

　Better Thermal Dissipation of High Bandwidth Memory (SK Hynix)

Session 27: Next Generation Wafer-to-Wafer Copper Bonding
・Paper 1. 0.5 µm Pitch Next Generation Hybrid Bonding with High Alignment

　Accuracy for 3D Integration(TEL America)
・Paper 2. Low Temperature and Fine Pitch Nanocrystalline Cu/SiCN

　Wafer-to-Wafer Hybrid Bonding(ITRI/ Nanya Technology)
・Paper 3. 0.5 µm Pitch Wafer-to-Wafer Hybrid Bonding with SiCN Bonding

　Interface for Advanced Memory(AMAT/EVG)
・Paper 4. Fine-Pitch 30 µm Cu-Cu Bonding Using Electroless Nano-Ag (ASE)
・Paper 5. Influence of H2O in Bonding Interfaces on Bonding Strength of

　Plasma-Activated Bonded Silicon Oxide (Sony)

・Paper 7. A Study on Multi-Chip Stacking Process by Novel Dielectric Polymer

　Adhesive for Cu-Cu Hybrid Bonding (Mitsui Chemicals)

Session 31: MEMS Sensor, Bio, and Advanced Interconnect Reliability
・Paper 4. Development of High Reliability 6 μm-Pitch Cu-Cu Connections

　Using over-400 mm²-Large Chip on Wafer Bonding Process (Sony)

Session 32: Thermo-Mechanical Modelling and Characterization
・Paper 2. Simulation of device structure impacts on bonding wave and strain in

　Wafer-to-Wafer Cu-Cu Hybrid Bonding (Sony)

Session 34: Bonding Assembly - Novel Packaging, Process, and Characterization
・Paper 2. Contamination-Free Cu/SiCN Hybrid Bonding Process Development

　for Sub-µm Pitch Devices with Enhanced Bonding Characteristics (Samsung)
・Paper 3. Integration and Process Challenges of Self Assembly Applied to

　Die-to-Wafer Hybrid Bonding(CEA-LETI/Intel)
・Paper 4. Critical Dimension Scatterometry as a Scalable Solution for Hybrid

　Bonding Pad Recess Metrology(Intel/KLA) 
・Paper 5. A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer

　Warpage (imec/EVG)
・Paper 7. Impact of Thermal Annealing and Other Process Parameters on

　Hybrid Bonding Performance for 3D Advanced Assembly Technology

　(Intel/Yield Engineering Systems)

Interactive Presentations:
・Paper 37-1. Investigation of Cu-to-Cu and Oxide-to-Oxide Bonding

　(Seoul National University of Science and Technology)
・Paper 37-6. Surface Modification on Hydrophilicity Enhancement Using

　NH4OH, NaOH and KOH on Fine-Pitch Low Temperature Cu/SiO2 Hybrid

　Bonding (National Chiao Tung University/ITRI)

・Paper 38-6. 50 nm Overlay Accuracy for Wafer-to-Wafer Bonding by

　High-Precision Alignment Technologies (Nikon)
・Paper 38-7. Multi-Stack Hybrid Cu Bonding Technology Development Using

　Ultra-Thin Chips (Samsung)
・Paper 38-8. An Investigation on Particle Embedding Capability of Wafer Level

　Spin-on Polymer Underfill Enabling Low Temperature Bonding of Hybrid Bonding

　System (JSR/imec)
・Paper 38-11. Selective Self-Assembled Monolayer for Copper Surface Protection

　During Plasma Activation of Hybrid-Bonded Wafers (TEL America)
・Paper 38-15. Chip-to-Chip Hybrid Bonding with Larger-Oriented Cu Grains for

　µ-Joints Beyond 100 K(Tohoku University/JCU)

・Paper 38-27. Novel Polymer-Based Ultra-High Density Bonding

　Interconnection (National Tsing Hua University/ITRI/DuPont)
・Paper 40-4. A Thermally Friendly Bonding Scheme for 3D System

　Integration (TSMC)

・Paper 40-13. Optimization of the Cu Microstructure to Improve Copper-to-

　Copper Direct Bonding for 3D Integration (Atotech)
・Paper 40-22. High Temperature Storage of Cu-Cu Joints Fabricated by Highly

　(111)-Oriented Nanotwinned Cu (National Yang Ming Chiao Tung University)

4．その他注目論文 7件
Session 19: Advances in 3D Integration and Hybrid Bonding
・Paper 2. Electrical and Thermal Analysis of Bumpless Build Cube 3D Using

　Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing (Tokyo Tech)

Session 28: Process Enhancements in 3D, FOWLP, and TSV Technologies
・Paper 7. Next Generation Infrared (IR) Laser Debonding / Silicon Handle

　Technology for Precision Chiplet Technology Applications (IBM/TEL)

Session 30: Trends in Encapsulants and Low Dk/Df Dielectrics
・Paper 5. Novel Photo-Definable Low Dk & Df Polyimide for Advanced Package

　of High Frequency Application(Toray)
・Paper 6. Novel Low Df Thermosetting Film and Photo Imageable Film (Taiyo Ink)

Session 33: Advances in RDL, Via, and TSV Technologies for Chiplet Integration
・Paper 5. Development of a Plasma Etching Process of Copper for the

　Microfabrication of High-Density Interconnects in Advanced Packaging

　(University of Sherbrooke/IBM Canada)
・Paper 7. Fine Pitch Micro Via Interconnection with Reliable Electroless/Electric

　Cu Plating Layers Combined with High Power DUV Picosecond Laser for Organic

　Substrates (Osaka University/Okuno Chemical/Spectronix)

Interactive Presentations:
・Paper 38-29. Formation and 3D Stacking Process of CMOS Chips with Backside 

　Buried Metal Power Distribution Networks (AIST/Kobe University)

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